Integrated multiplexer/de-multiplexer for active-matrix display/imaging arrays

ABSTRACT

This invention presents Vt-shift invariant integrated multiplexer and de-multiplexer circuits that can be fabricated with a-Si:H, poly-crystalline silicon, or organic/polymer TFTs. The de-multiplexer and multiplexer includes a plurality of TFTs which are connected in series, and a drive TFT. These circuits are used with active matrix displays to control the gate addressing, and with imaging arrays to multiplex the read-out data.

FIELD OF THE INVENTION

This invention relates in general to an apparatus for reading and/orwriting data in active matrix display and imaging arrays. The activematrix can be derived from both inorganic and organic materials that areamorphous or polycrystalline.

BACKGROUND OF THE INVENTION

The most popular addressing method in large area displays is activematrix addressing where the gate and data lines form the rows andcolumns of the grid-like structure.

FIG. 1 is a diagram showing an active matrix array 100 of an activematrix display. The active matrix array 100 has a plurality of pixels106. The pixels are controlled by transistors in the electronicbackplane. The active matrix array has at least one transistor per pixelthat acts as an analog switch. The switching transistor either enablesor disables writing of data to that pixel. In FIG. 1, Thin FilmTransistor (TFT) 108 is shown as the switching transistor, which isconnected to a data line 102 and a gate line 104. The switchingtransistors of the display array are controlled by a de-multiplexer(also known as a gate driver). The purpose of the gate driver is tosequentially activate every row of the display while data is beingwritten to that row. This data is stored and retained by the activepixels until they get new data in the next frame. This method of writingdata to a display array is known as row-by-row addressing.

Currently, amorphous silicon (a-Si:H), polycrystalline silicon, ororganic/polymer materials can be used for making the switchingtransistors in display pixels.

In a-Si:H and polycrystalline silicon, the TFTs suffer fromelectrical-stress induced meta-stability problems. Therefore, they arenot usually used in the implementation of the driving circuitry.

However, if the metastability problems can be overcome, there aresignificant benefits including cost savings in implementing integratedgate drivers on the display instead of having external chips.

It is also desirable to provide a gate multiplexers/de-multiplexers thatcan also be integrated with active-matrix imaging arrays, where theimaging pixels are activated row-by-row during image read-out.

SUMMARY OF THE INVENTION

The objective of this invention is to provide an integrated gatede-multiplexer and read-out multiplexer that can be integrated on to aa-Si:H, poly-crystalline silicon, or organic/polymer display or imagingarrays. Further, it is an object of the present invention to provide anintegrated gate de-multiplexer and read-out multiplexer that overcomesthe material metastability, and has threshold voltage (Vt-shift)invariant operation over the lifetime of the array.

In accordance with an aspect of the present invention, there is provideda drive circuit for driving a pixel array, which includes an outputterminal for driving a transistor in a pixel array, a drive transistorfor transferring a gate selecting signal to the output terminal, and oneor more control transistors for switching the drive transistor inresponse to one or more control signals. The drive transistor, thecontrol transistors and the transistor in the pixel array are thin filmtransistors.

In accordance with a further aspect of the present invention, there isprovided a driver for driving a pixel array. The pixel array includes aplurality of gate lines, each of which is connected to a gate of aswitching transistor. The driver includes a plurality ofde-multiplexers, each of which drives a corresponding gate line in apixel array, and one or more control signal lines for activating thede-multiplexers. The de-multiplexer includes an output terminalconnected to the corresponding gate line in the pixel array, a drivetransistor for transferring a gate selecting signal to the outputterminal, and one or more control transistors for switching the drivetransistor in response to control signals from the control signal lines.The drive transistor, the control transistors and the switchingtransistor in the pixel array are thin film transistors.

In accordance with a further aspect of the present invention, there isprovided a read circuit for reading data from a data line in a pixelarray. The read circuit includes an input terminal connected to a dataline in a pixel array, data in the pixel array transferred to the dataline by a transistor in the pixel array, an output terminal, a drivetransistor for transferring the data to the output terminal and one ormore control transistors for switching the drive transistor in responseto one or more control signals. The drive transistor, the controltransistors and the transistor in the pixel array are thin filmtransistors.

In accordance with a further aspect of the present invention, there isprovided a read circuit for reading data from an pixel array. The pixelarray includes a plurality of data lines, each of which is connected toa transistor for transferring data to the data line. The read circuitincludes a plurality of multiplexers, each of which is connected to adata line in a pixel array and one or more control signal lines foractivating the multiplexers. The multiplexer includes an input terminalconnected to a corresponding data line in the pixel array, an outputterminal, a drive transistor for transferring the data to an outputterminal and one or more control transistors for switching the drivetransistor in response to one or more control signals. The drivetransistor, the control transistors and the transistor in the pixelarray are thin film transistors.

In accordance with a further aspect of the present invention, there isprovided a drive circuit for driving a pixel array, which includes apull up network circuit for pulling up a gate voltage of a switchingtransistor in a pixel array in response to a gate selecting signal, anda pull down network circuit for pulling down the gate voltage inresponse to one or more control signals. The pull down network circuitincludes one or more transistors. The transistors of the pull downnetwork circuit and the switching transistor are thin film transistors.

According to the invention, gate de-multiplexers and read-outmultiplexers can be integrated into arrays, such as active-matrixdisplay/imaging arrays, and the integrated gate de-multiplexers andread-out multiplexers can ensure stability of the transistor.

Other aspects and features of the present invention will be readilyapparent to those skilled in the art from a review of the followingdetailed description of preferred embodiments in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be further understood from the following descriptionwith reference to the drawings in which:

FIG. 1 is a schematic diagram showing a general active matrix array;

FIG. 2 is a block diagram showing a de-multiplexer circuit block 200 inaccordance with one embodiment of the present invention;

FIG. 3 is a circuit diagram showing one example of the de-multiplexercircuit block 200 of FIG. 2;

FIG. 4 is a schematic diagram showing an array driver 420 in accordancewith one embodiment of the present invention and a pixel array 410;

FIG. 5 is a diagram showing a threshold voltage shift of a TFT;

FIG. 6 is a diagram showing a threshold voltage shift of a TFT;

FIG. 7 is a timing chart showing operation of the de-multiplexer ofFIGS. 2, 3 and 4;

FIG. 8 is schematic diagram showing a de-multiplexer and an outputbuffer in accordance with one embodiment of the present invention;

FIG. 9 is a schematic diagram showing a pull-up/pull-down network basedde-multiplexer circuit 900 in accordance with another embodiment of thepresent invention;

FIG. 10 is a schematic diagram showing anther example of thede-multiplexer circuit 900 of FIG. 9;

FIG. 11 is a block diagram showing a multiplexer circuit block 1000 inaccordance with one embodiment of the present invention;

FIG. 12 is a circuit diagram showing one example of the multiplexercircuit block 1000 of FIG. 11;

FIG. 13 is a schematic diagram showing a read circuit 1120 in accordancewith one embodiment of the present invention and an imaging array 1110;

FIG. 14 is a circuit diagram showing a pull-up/pull-down network basedmultiplexer circuit 1000;

FIG. 15 is a schematic diagram showing a multiplexer and an outputbuffer in accordance with one embodiment of the present invention;

FIG. 16 is a block diagram showing one configuration of cascadedmultiplexers block 1500 in accordance with one embodiment of the presentinvention;

FIG. 17 is a block diagram showing one configuration of cascadedde-multiplexers block 2500 in accordance with one embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A gate de-multiplexer circuit block 200 in accordance with oneembodiment of the present invention is presented in FIG. 2. The gatede-multiplexer circuit block 200 has terminals V1 and V2, controlterminals A, B and C and an output terminal V-Out. As described below,the output terminal V-Out may be connected to a gate line that activatesa switching transistor of a pixel. The gate de-multiplexer circuit block200 includes a plurality of TFTs, which may be a-Si:H, poly-crystallinesilicon, or organic/polymer TFTs. The TFTs are connected in series, andwhose gate terminals are controlled by external control signals A, B,and C. The gate de-multiplexer 200 can be fabricated on the pixelarrays.

FIG. 3 shows one example of the gate de-multiplexer circuit block 200 ofFIG. 2. In FIG. 3, the gate de-multiplexer includes TFTs 302, 304 and306 that are connected in series.

The gates of the TFTs 302, 304 and 306 are connected to the controllines A, B, C, respectively. Only 3 TFTs 302, 304 and 306 and 3 controlsignals A, B and C are shown in FIG. 3. However, the gate de-multiplexermay have any number of TFTs which receive corresponding control signals.The number of TFTs and control signals ‘N’ is determined by the numberof rows in a display array, and is given by N=log2 [number of rows]. Thenumber of columns in the array does not determine the gatede-multiplexer size.

Pulsed voltage V1 is applied at one end of the series of TFTs, and theother end drives the gate of a relatively large drive TFT 308. The drainof the TFT 308 is connected to a pulsed voltage V2, and its sourceterminal Vout is connected to one row line of the array. In FIG. 3,“310,” denotes a capacitance of a selected line.

FIG. 4 shows an array driver 420 in accordance with one embodiment ofthe present invention and a pixel array 410. The pixel array-410includes a plurality of pixels (not shown), a plurality of switchingtransistors 414 and row lines (gate lines) 412A, 412B, . . . , 412H,each of which selects a corresponding switching transistor 414. Thearray driver 420 may be fabricated on the array 410.

The array 410 may be a a-Si:H, poly-crystalline silicon, ororganic/polymer display or imaging arrays.

The array driver 420 has one or more de-multiplexer circuit block. Eachrow line in the array 410 is connected to one gate de-multiplexercircuit block. As shown in FIG. 4, in the case of an array with 8 rows,the array driver 420 includes 8 de-multiplexer circuit blocks 200A,200B. . . . , 200H and 3 control lines are provided to the array driver420.

In FIG. 4, V1 denotes an address signal and V2 denotes a gate selectingsignal. One V1 line and one V2 line are provided to all de-multiplexercircuit blocks. However, a plurality of V1 lines and V2 lines may beprovided to the de-multiplexer circuit blocks. Each de-multiplexercircuit block may include a circuit similar to the de-multiplexer 200shown in FIG. 3.

Each de-multiplexer circuit block is controlled by either A, B, or C, ortheir complements /A, /B, /C as shown in FIG. 4. The control signals areactivated such that only one de-multiplexer circuit block will befunctional atone time, and each one will be turned on and off insequence. The control signals are square waves of different frequenciessuch that their logic levels follow the binary count from 000 to 111.

For example, the de-multiplexer circuit block 200H is turned “ON” whenthe control signals A, B, and C are all at logic ‘high’. At this point,voltage V1 is transmitted to the gate of the drive transistor (e.g. TFT308 in FIG. 3). Voltage V1 is a pulsed source. When V1 is ‘high’, thedrive TFT (308) is turned “ON”. At that point, voltage V2 will bewritten to the corresponding row (e.g. 412H) of the array. The pulsewidth of V2 is long enough to allow time for data to be written to thecorresponding row of the array. Once the data writing operation iscomplete, V2 becomes ‘low’, thus pulling down the voltage on the rowline. After that V1 also becomes ‘low’, thus pulling down the gatevoltage of the drive TFT (308). Subsequently the one or more of thecontrol signals can change, so that the series connected TFTs (302 to306) do not allow V1 to be written to the gate of the drive TFT (308).

Threshold Voltage Stability:

The threshold voltage (V_(t)) of a TFT changes when it is underprolonged gate bias stress. TFTs show different threshold voltage shiftbehaviour under positive and negative gate bias stress as shown in FIG.5 and FIG. 6. In FIGS. 5 and 6, “Vst” denotes a gate bias stress and“Vth” denotes a threshold voltage of a TFT.

The Vt increases with respect to the positive stress voltage as well asthe stress duration. However, Vt can be decreased by applying largenegative voltages to the gate of the TFT. Hence, to prevent the Vt ofany TFT from increasing, it is desirable that the TFT experiencesnegative bias stress such that it is equal and opposite to the positivebias stress that it experiences.

In the de-multiplexer circuit of the embodiment of the presentinvention, this is ensured by making the gate voltage of all TFTsnegative when they are in the “OFF” state. This means that V1, V2, andthe control signals are at a negative voltage in logic state ‘low’, andat a positive voltage in logic state ‘high’.

FIG. 7 is a timing chart showing the operation of one de-multiplexercircuit block in accordance with one embodiment of the presentinvention. FIG. 7 shows the relative voltage levels of all input andoutput signals, along with their duty cycles. “H” denotes a logic state“high”, and “L” denotes a logic state “low”. V1, V2, and the controlsignals are at a negative voltage in logic state “L”, and at a positivevoltage in logic state “H”.

In the de-multiplexer circuit of the embodiment of the presentinvention, the switching TFTs (e.g., TFTs 302,304, 306 in FIG. 3) are“ON” 50% of the time because the control signals have a duty cycle of50%. V1 appears at the gate of the drive TFT (e.g. TFT 308 in FIG. 3)only once per frame (T0-T1). “Frame” refers to the writing/reading ofone set of image information to/from the array. Hence the drive TFT willexperience negative bias stress for the rest of the time. Similarly, V2is transmitted to any particular row line of the array only one perframe. These duty cycles ensure that the Vt of none of the transistorswill increase during operation of the de-multiplexer.

Addition of an Output Buffer:

An output buffer can be added at the output of each de-multiplexercircuit block. FIG. 8 shows the de-multiplexer 200 and an output buffer810 connected to the de-multiplexer 200. The output buffer 810 isconnected to the source terminal of the drive TFT 308.

The output terminal V-Out may be connected to the input of the outputbuffer 810. The output buffer 810 may be included in the de-multiplexcircuit block 200. The output buffer 810 may include an a-Si:H,poly-crystalline silicon, or organic/polymer TFT.

This buffer 810 allows the drive TFT 308 to rapidly raise or lower therow line voltage to the desired level even if the row line capacitancesare very high.

Variation of the Multiplexer Architecture:

FIG. 9 shows a de-multiplexer circuit 900 in accordance with antherembodiment of the present invention. The de-multiplexer 900 in FIG. 9has a pull-up network 910, a pull-down network 920. The three seriesTFTs in FIG. 3 are replaced by the pull-up network 910 including aresistor R, and the pull-down network 920 including three parallel TFTs902, 904 and 906. The TFTs 902, 904 and 906 may be a-Si:H,poly-crystalline silicon, or organic/polymer TFTs.

The resistor R is connected between V1 and the terminal V-Out, and eachof the TFTs 902, 904 and 906 is connected between the terminal V-Out anda ground.

Three control signals A, B and C are supplied to the gates of the TFTs902, 904 and 906, respectively. A pulsed voltage is applied to theterminal V2.

The output terminal VOut may be connected to the gate line (e.g., 412Hin FIG. 4) in the array (410 in FIG. 4). V2 may be negative when it isin a logic state “low”. That ensures the threshold voltage stability asdescribed above.

The pull up network 910 allows the gate line voltage to be raised to thedesired positive voltage, and the pull-down network 920 allows the gateline voltage to be lowered to the desired negative voltage.

FIG. 10 shows another example of the de-multiplexer 900. In FIG. 10, theresistor R is replaced by a diode-connected TFT 912.

The de-multiplexer 900 of FIGS. 9 and 10 can be applied to the arraydriver 420 of FIG. 4 and can be integrated with the array 410 in FIG. 4.

Use of the De-Multiplexer Circuit as a Multiplexer

The de-multiplexer circuit architecture in accordance with theembodiments of the present invention can also be used to create amultiplexer.

A multiplexer circuit block 1000 in accordance with one embodiment ofthe present invention is shown in FIG. 11. The multiplexer circuit block1000 includes a plurality of TFTs, which may be a-Si:H, polycrystallinesilicon, or organic/polymer TFTs. The TFTs are connected in series, andwhose gate terminals are controlled by external control signals A, B andC. The multiplexer circuit block 1000 has an input terminal V-in, anoutput terminal V-Out, control terminals A, B and C and a terminal V1.The multiplexer 1000 can be fabricated on the array (e.g., 410 in FIG.4).

FIG. 12 shows one example of the multiplexer circuit block 1000 of FIG.11. The multiplexer 1000 in FIG. 12 includes TFTs 1002, 1004 and 1006that are connected in series. The TFTs 1002, 1004 and 1006 may bea-Si:H, poly-crystalline silicon, or organic/polymer TFTs. The TFTs1002, 1004 and 1006 are controlled by control signals A, B and C,respectively. In FIG. 12, TFTs 1002, 1004 and 1006 and control signalsA, B and C are shown. However, the multiplexer may have any number ofTFTs and the number of control signals is not limited.

This multiplexer is useful in imaging arrays during the read-out phase.The imaging array is one of active matrix array. In a-Si:H,poly-crystalline silicon or organic/polymer based imaging arrays,imaging pixels are activated row-by-row during image read-out. Duringthe read-out phase, image data is sent out serially using a multiplexeras described below.

The structure of the multiplexer is similar to that of thede-multiplexer shown in FIG. 3, except that the input signal V2 is nowdifferent. The drain of the drive TFT 1008 is connected to the source ofthe TFT in the imaging array pixel, and will be supplied with a datavoltage from the pixel.

Pulsed voltage V1 is supplied to one end of the series of TFTs (i.e.,TFT 1002) and the other end drives the gate of a transistor 1008. Thetransistor 1008 is a relatively large drive TFT. The drive TFT 1008maybe an a-Si:H, poly-crystalline silicon, or organic/polymer TFT. Thedrain of the TFT 1008 is connected to a terminal V-in. The V-in isconnected to a data line in an imaging array as described below. Thesource of the TFT 1008 is connected to an output terminal V-Out.

FIG. 13 shows showing a read circuit 1120 in accordance with oneembodiment of the present invention and an imaging array 1110. Theimaging array 1110 includes a plurality of pixels (not shown), a dataline 1112A, 1112B, . . . , 1112H and a transistor 1114.

The imaging array 1110 may be a a-Si:H, poly-crystalline silicon, ororganic/polymer TFTs based imaging array and the transistor 1114 may bean a-Si:H, polycrystalline silicon, or organic/polymer TFT.

The source of the TFT 1114 is connected to a corresponding data line.Each data line in the array 1110 is connected to one multiplexer circuitblock. As shown in FIG. 13, in the case of an array with 8 data lines, 8multiplexer circuit blocks 1000A, 1000B, . . . , 1000H and 3 controllines are provided to the read circuit 1120. Each multiplexer is similarto the multiplexer 1000 shown in FIG. 12. “VA”, “VB” . . . , “VH” inFIG. 13 correspond to “V-in” in FIGS. 11 and 12.

A combination of control signals A, B, and C activates one multiplexercircuit block. That circuit block will now allow V1 to appear at thegate of the drive TFT (e.g., TFT 1008 in FIG. 12). When V1 is ‘high’,the drive TFT (1008) allows the image data voltage to appear at theoutput. When V1 becomes ‘low’, the drive TFT (1008) is in the “OFF”state. To avoid Vt increases in the drive TFT (1008) over a period oftime, V1 is negative when it is in logic state “low” and V1 is positivewhen it is in logic state “high”. Also, the control signals are at anegative voltage in logic state “low”, and at a positive voltage inlogic state “high”. For example, the multiplexer is operated by V1, A, Band C shown in FIG. 7.

Variation of the Multiplexer Architecture:

FIG. 14 shows anther example of the multiplexer circuit 1000 of FIG. 11.The multiplexer 1000 in FIG. 14 has a pull-up network 1210, a pull-downnetwork 1220 and the drive TFT 1008. In order to increase the switchingspeed, the three series TFTs (1002 to 1006) in FIG. 12 have beenreplaced by the pull-up network 1210 including a resistor R, and thepull-down network 1220 including three parallel TFTs 1202, 1204 and1206. The TFTs 1202, 1204 and 1206 may be a-Si:H, poly-crystallinesilicon, or organic/polymer TFTs.

The resistor R is connected between V1 and the gate of the drive TFT1008, and each of the TFTs 1202, 1204 and 1206 is connected between thegate of the drive TFT 1008 and a ground.

A, B, and C are the three control signals, which are supplied to thegates of the TFTs 1202, 1204 and 1206, respectively. V1 is a pulsedvoltage that is negative when it is ‘low’. Also, the control signals A,B and C are negative when it is “low”. That ensures that the Vt of thetransistors will not increase during operation of the multiplexer.

V-in terminal is connected to the data line (e.g., the data line 1112Ain FIG. 13) that needs to be multiplexed. The operation of this circuitis similar to that of the circuit in FIG. 12 except that the time delayin switching the drive TFT 1008 on or off has been substantiallyreduced. In this circuit, the resistor R can also be replaced by adiode-connected TFT.

Addition of an Output Buffer:

An output buffer can be added at the output of each multiplexer circuitblock. FIG. 15 shows the multiplexer 1000 and an output buffer 1110connected to the multiplexer 1000. The output buffer 1110 is connectedto the source terminal of the drive TFT 1008.

The output terminal V-Out is connected to the output of the outputbuffer 1110. The output buffer 1110 may be included in the multiplexcircuit block 1000L The output buffer 1110 may include an a-Si:H,poly-crystalline silicon, or organic/polymer TFT.

The output buffer 1110 allows the drive TFT 1008 to rapidly raise orlower the row line voltage to the desired level.

Cascading of Multiplexers/De-Multiplexers to Reduce Vt-Shifts:

In order to further reduce the effect of gate bias stress on TFTs in themultiplexer/de-multiplexer circuits presented here, the individualblocks can be cascaded to form a larger unit.

FIG. 16 shows a cascaded multiplexers block 1500 in accordance with oneembodiment of the present invention. In FIG. 16, the cascadedmultiplexers block 1500 includes a front-process block 2000 includingmultiplexers 1000X, 1000Y, 1000Z, and a multiplexer 1000W. Themultiplexers 1000X to 1000W may be similar to that of FIGS. 12, 14 or15.

In the front-process block 2000, each multiplexer is activated inresponse to a combination of the control signals A, B and C and theircomplements /A, /B and /C. In the front-process block 2000, onemultiplexer is activated depending on the combination of the controlsignals.

The input V-in of the multiplexer 1000W receives the outputs of themultiplexers 1000X to 1000Z. The multiplexer 1000W receives the controlsignals through a control circuit 2020. The multiplexer 1000W isactivated when any one of the multiplexers in the front-process block2000 is activated.

FIG. 17 shows a cascaded de-multiplexers block 2500 in accordance withone embodiment of the present invention. In FIG. 17, the cascadedde-multiplexers block 2500 includes a de-multiplexer 3000W and apost-process block 4000 including de-multiplexers 3000X, 3000Y and3000Z. The de-multiplexers 3000X to 3000W may be similar to that ofFIGS. 3 and 8 to 10.

In the post-process block 4000, each de-multiplexer is activated inresponse to a combination of the control signals A, B and C and theircomplements /A, /B and /C. In the post-process block 4000, onede-multiplexer is activated depending on the combination of the controlsignals.

The de-multiplexer 3000W receives the control signals through thecontrol circuit 2020. The multiplexer 3000W is activated when any one ofthe de-multiplexers in the post-process block 4000 is activated. Theoutput V-Out of the de-multiplexer 3000W is supplied to V2 terminals ofthe de-multiplexers 3000X to 3000Z.

In cascaded multiplexers and de-multiplexers, only one path is in ON atany given time. Thus, the TFTs in the OFF paths will have a negativegate bias and will have enough time to recover from any Vt-shift thatmay have occurred.

The de-multiplexer and the multiplexer in accordance with theembodiments of the present invention can apply to a-Si:H,polycrystalline silicon, and organic/polymer thin film transistoractive-matrix arrays. Further, the de-multiplexer and the multiplexercan be fabricated on the arrays.

Numerous modifications, variations and adaptations may be made to theparticular embodiments of the invention described in the documentsattached herein, without departing from the scope of the invention,which is defined in the claims.

1. A drive circuit for driving a pixel array, the drive circuitcomprising: an output terminal for driving a transistor in a pixelarray; a drive transistor for transferring a gate selecting signal tothe output terminal; and one or more control transistors for switchingthe drive transistor in response to one or more control signals, thedrive transistor, the control transistors and the transistor in thepixel array being a thin film transistor.
 2. The drive circuit asclaimed in claim 1, wherein the control transistors are connected inseries between a terminal receiving a switching signal and the gate ofthe drive transistor.
 3. The drive circuit as claimed in claim 2 furthercomprising an output buffer connected to the source terminal of thedrive transistor, the drain terminal of the drive transistor receivingthe gate selecting signal.
 4. The drive circuit as claimed in claim 2,wherein each of the control signals has a duty cycle of 50%.
 5. Thedrive circuit as claimed in claim 3, wherein each of the controlsignals, the switching signal and the gate selecting signal is at anegative voltage in a logic state “low”, and each of the controlsignals, the switching signal and the gate selecting signal is at apositive voltage in a logic state“high”.
 6. The drive circuit as claimedin claim 1, wherein the thin film transistor is derived from aninorganic or organic/polymer material.
 7. The drive circuit as claimedin claim 6, wherein the thin film transistor is an amorphous silicontransistor or a polycrystalline silicon transistor.
 8. (Cancelled) 9.The driver as claimed in claim 1 wherein the driver includes: aplurality of de-multiplexers, each of which drives a corresponding gateline in the pixel array; and one or more control signal lines foractivating the de-multiplexers, the de-multiplexer including: the outputterminal connected to the corresponding gate line in the pixel array;the drive transistor; and one or more control transistors for switchingthe drive transistor in response to the control signals from the controlsignal lines.
 10. The driver as claimed in claim 9, wherein thede-multiplexer is integrated with the pixel array. 11-14. (Cancelled)15. The driver as claimed in claim 9, wherein the control signal linesare activated such that only one de-multiplexer is activated at onetime. 16-18. (Cancelled)
 19. A read circuit for reading data from a dataline in a pixel array, the read circuit comprising: an input terminalconnected to a data line in a pixel array, data in the pixel arraytransferred to the data line by a transistor in the pixel array; anoutput terminal; a drive transistor for transferring the data to theoutput terminal; and one or more control transistors for switching thedrive transistor in response to one or more control signals, the drivetransistor, the control transistors and the transistor in the pixelarray being a thin film transistor.
 20. The read circuit as claimed inclaim 19, wherein the control transistors are connected in seriesbetween a terminal receiving a switching signal and the gate of thedrive transistor.
 21. The read circuit as claimed in claim 20, whereineach of the control signals has a duty cycle of 50%.
 22. The readcircuit as claimed in claim 20, wherein each of the control signals andthe switching signal is at a negative voltage in a logic state “low”,and is at a positive voltage in a logic state “high”.
 23. The readcircuit as claimed in claim 19 further comprising a pull up networkcircuit for pulling up a gate voltage of the drive transistor inresponse to a switching signal. 24-25. (Cancelled)
 26. The read circuitas claimed in claim 23, wherein the control transistors are connectedbetween the gate of the drive transistor and a ground.
 27. The readcircuit as claimed in claim 23 further comprising an output buffer forreceiving a signal on the input terminal.
 28. The read circuit asclaimed in claim 19, wherein the thin film transistor is derived from aninorganic or organic/polymer material.
 29. The read circuit as claimedin claim 19, wherein the thin film transistor is an amorphous silicontransistor or a poly-crystalline silicon transistor.
 30. (Cancelled) 31.The read circuit as claimed in claim 19, wherein the pixel arrayincluding a plurality of data lines, each of which is connected to atransistor for transferring data to the data line, the read circuitcomprising: a plurality of multiplexers, each of which is connected to adata line in a the pixel array; and one or more control signal lines foractivating the multiplexers, the multiplexer including: the inputterminal connected to a corresponding data line in the pixel array; theoutput terminal; the drive transistor; and the one or more controltransistors for switching the drive transistor in response to the one ormore control signals.
 32. The read circuit as claimed in claim 31,wherein the multiplexer is integrated with the pixel array.
 33. The readcircuit as claimed in claim 31, wherein the control transistors areconnected in series between a terminal receiving a switching signal andthe gate of the drive transistor. 34-35 (Cancelled)
 36. The read circuitas claimed in claim 31, wherein the multiplexer further comprises a pullup network circuit for pulling up a gate voltage of the drive transistorin response to a switching signal. 37-39. (Cancelled)
 40. The readcircuit as claimed in claim 36, wherein the multiplexer furthercomprises an output buffer for receiving a signal on the input terminal.41. The read circuit as claimed in claim 31, wherein the control signallines are activated such that only one multiplexer is activated at onetime.
 42. The read circuit as claimed in claim 31, wherein the thin filmtransistor is derived from an inorganic or organic/polymer material. 43.The read circuit as claimed in claim 31, wherein the thin filmtransistor is an amorphous silicon transistor or a polycrystallinesilicon transistor.
 44. (Cancelled)
 45. The drive circuit as claimed inclaim 1 further comprising a pull up network circuit for pulling up thegate line voltage and/or a pull down network circuit for pulling downthe gate line voltage.
 46. (Cancelled)
 47. The driver as claimed inclaim 9, wherein the de-multiplexer further comprising a pull up networkcircuit for pulling up the gate line voltage and/or a pull down networkcircuit for pulling down the gate line voltage.
 48. (Cancelled)
 49. Adrive circuit for driving a pixel array, the drive circuit comprising: apull up network circuit for pulling up a gate voltage of a switchingtransistor in a pixel array in response to a gate selecting signal; anda pull down network circuit for pulling down the gate voltage inresponse to one or more control signals; the pull down network circuitincluding one or more transistors, the transistors of the pull downnetwork circuit and the switching transistor being a thin filmtransistor.
 50. The drive circuit as claimed in claim 49, wherein thetransistors of the pull down network circuit are connected between aterminal which is connected to the gate of the switching transistor anda ground. 51-52. (Cancelled)
 53. The drive circuit as claimed in claim49, wherein the control signals are at a negative voltage in a logicstate “low”.
 54. The drive circuit as claimed in claim 49, wherein thegate selecting signal is at a negative voltage in a logic state “low”.